The present invention relates to a column decoder of a semiconductor memory apparatus; and, more particularity, to a column decoder for low power consumption in the semiconductor memory apparatus.
Generally, a semiconductor memory apparatus includes a plurality of bit lines and word lines for storing data in a plurality of cells and reading out stored data from the cells, a selection circuit for selecting one of the plurality of bit lines and word lines, and a peripheral circuit, such as a plurality of sense amplifiers.
To select a cell of the memory device, the semiconductor memory apparatus also includes a row decoder, which produces a word line select signal XI to select a word line by decoding row address signals, and a column decoder, which produces a column select signal YI to select a bit line by decoding column address signals.
FIG. 1 is a circuit diagram illustrating a conventional driver for producing a column select signal YI in a column decoder.
Referring to FIG. 1, in the case where a column decoder does not operate, all the input signals are at a logic low level. In the case where the column decoder operates, signals YA345C and YA678C of the column select signals are at a logic high level and, when any of the signals YA12P<0>, YA12P<1>, YA12P<2> and YA12P<3> go to a logic high level, their respective column select signals YI<0>, YI<1>, YI<2> and YI<3> are enabled.
Since the circuit block described above is selected by column select control signals YA345C<0:7> and YA678C<0:7>, the semiconductor memory apparatus shown in FIG. 1 can have 256 number of column select signals YIs, e.g., YI<0:255>. As shown in FIG. 1, a driver to produce a column select signal YI in the conventional memory device comprises an inverter using an external voltage VDD and a ground voltage VSS as operating voltage sources.
The driver to produce a column select signal YI which is representative one of all column select signals, comprising an inverter using the external voltage VDD and the ground voltage VSS as the operating voltage sources, has a large size because of a large load applied thereto. Moreover, the drivers to produce the column select signals YI, comprising inverters using the external voltage VDD and the ground voltage VSS as the operating voltage sources, occupy a significant area of a semiconductor memory apparatus because the drivers are disposed in an array structure to produce the column select signals YI.
For example, in the case of a 512M DRAM, it requires the driver to produce the column select signals YI of 16×1024. Assuming that a width of a PMOS transistor, which is employed in a driver to produce the column select signal YI, is approximately 40 μm, a theoretical total width of the PMOS transistors employed in the driver to produce the column select signal YI is approximately 655360 μm in the abstract. Substantially, since all plural MOS transistors in the driver are not formed on the same plane and parts of the plural MOS transistors can be overlapped, a practical total width of the PMOS transistors employed in the driver inside a chip of the semiconductor memory apparatus is very smaller than above theoretical total width.
Furthermore, assuming that a leakage current of the PMOS transistor which is employed in driver to produce the column select signal YI is approximately 50 pA/μm, the total amount of leakage current caused by the driver for producing the column select signal YI becomes approximately 33 μA. This is 20% of the entire IDD 2P value. Here, the IDD 2P, as a specification of a precharge standby DC current of the semiconductor memory apparatus, defines an amount of the current consumed in a power down mode. 20% is a substantial portion of the entire IDD 2P value, and can have an effect on the yield of low power mobile DRAMs.